Monday, 26 March 2007

DRAM now and future

(photo quoted from
Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. Its advantage over SRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density. Since DRAM loses its data when the power supply is removed, it is in the class of volatile memory devices.(Wikipedia)

What would make a good memory subsystem?
1. High bank counts aids multitasking in multi-core CPUs,
2. High memory bandwidth to keep up demands from CPU and graphic engines.
3. Low latency reduces stall time for CPU in case of Cache miss.
4. High memory capacity reduces HD access.
5. Low power to reduce cooling cost

Application oriented market segmentation in 10 years
1. Commodity DRAM: x16 graphic, x8 desktop, x4 enterprise server.
2. Low Power DRAM: Handset, mobile phone.
3. Graphic DRAM: high and graphic system

DRAM design trend and challenges
1. More features to accommodate system variation and requirements
2. More design facilities to accommodate signal skew
3. Future DRAM considerations
4. Power dissipation is number 1 DRAM design objective.1.
5. Challenge in high frequency design in bulk CMOS technology.
6. High efficiency voltage regulator design.
7. High speed clock tree with very low jitter spec under noisy environment
8. Keep same power with very low jitter spec under noisy environment.
9. Package design and electrical modeling1.

1. Memory design has to start from system perspective.
2. High speed and robust design requires design innovation
3. Low cost and higher density DRAM with constant power budget will continue to be the main deriving force.

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